PSM Logic Functions, Flip-Flop Block Function - GF54.21-D-3211TSA

Model 907 

with code ED5 (Parameterisable special module) 

Flip-flop block function 

The flip-flop block has two inputs:

• an analog input 1 (E₁ ) (16 bit) for set (S) or data (D)
• a digital (binary) input 2 (E₂ ) for reset (R) or clock (C)

The flip-flop block has an analog output (A_A ) (16 bit) and a digital (binary) output (A_B ).

Output (A_B ) represents the logical inversion of output (A_A ).

Coding of flip-flop block 

The flip-flop block can be configured either as a "D flip-flop" with data and clock input, or as an "RS flip-flop" with set and reset input.

When configured as a "D flip-flop", it is possible to save 16-bit signals at input 1 (E₁ ) and to output them at output (A_A ).

Signal identification number = Signal ID.

Designation in data entry table	Data entry bit width	Data bit evaluation	Meaning
B1_G1_FF1_type	1 bit	-	Adjustment value: "RS flip-flop" → 0 "D flip-flop" → 1
B1_G1_FF1_evaluation	1 bit		Adjustment value with "RS flip-flop": state-triggered → 0 edge-triggered →1 Adjustment value with "D flip-flop": positive edge evaluation → 0 negative edge evaluation → 1
B1_G1_FF1_1_signal_ID	32 bit	1 bit: "RS flip-flop" 16 bit: "D flip-flop"	Filter + reference ID of set (S) or data (D) input signal
B1_G1_FF1_2_Signal_ID	32 bit	1 bit	Filter + reference ID of reset (R) or clock (C) input signal

Designation in signal ID list	Data bit width	Meaning
Out_G1_FF1	16 bit	Signal ID of output (AA )
Out_G1_FF1_inv	1 bit	Signal ID of output (AB ) (corresponds to logically inverted output (AA ))

The same applies for the other flip-flop blocks with the naming conventions:

• "B<block number>_G<group number>_FF<number> ..."
• "Out_G<group number>_FF<number> ..."

Overview of system components for parameterizable special module (PSM)

GF54.21-D-9998TSA