PSM Logic Functions, Counter Block Function - GF54.21-S-3213TRA

Model 447 

With Code ED5 (Parameterisable special module) 

Except Code XM7 (MOPF II) 

Model 448 

With Code ED5 (Parameterisable special module) 

Except Code XM7 (MOPF II) 

Courtesy of MERCEDES-BENZ USA

Counter block, function 

The counter block is an element which counts edge changes. It has a reset input (R), an activate (enable) input (En), an up/down direction input (U/D) and a counter input (ZE) to which the signal to be monitored can be applied.

A codable filter is connected upstream of each input (E₁ , E₂ , E₃ , E₄ ).

The internal counter register is 16 bits wide. When the reset input (R) is active, the content of this counter register is reset to the set reset value (RW) (e.g. 0x0000).

If the counter reading (ZS) increases to 0xFFFF, the reading overruns to 0x0000 the next time the edge of the clock input is reached. The activate (enable) input (En) enables or disables evaluation of the counter input (ZE).

The direction input determines the counting direction: With "0" at the input (E₄ ), counting will be upward; with "1", counting will be downward. Only positive edges are evaluated.

Coding of counter block 

The inputs (E₁ , E₂ , E₃ , E₄ ) of the counter block are coded as follows: The input (E₁ , E₂ , E₃ , E₄ ) is assigned an identification number (ID) of a signal in the signal pool. The counter reading (ZS) is written to the signal pool as a 16-bit value.

Designation in data entry table	Data entry bit width	Data bit evaluation	Meaning
B1_G1_CNT1_Reset value	16 bit	1 bit	Reset value (RW)
B1_G1_CNT1_1_Signal_ID	32 bit	1 bit	Filter + input signal data entry signal ID for reset(R) = "1"
B1_G1_CNT1_2_Signal_ID	32 bit	1 bit	Filter + input signal data entry signal ID for activate (enable) input (En) = 1.
B1_G1_CNT1_3_Signal_ID	32 bit	1 bit	Filter + input signal data entry signal ID for counter (ZE) → (edge evaluation)
B1_G1_CNT1_4_Signal_ID	32 bit	1 bit	Filter + signal ID for data entry of counting direction input signal: "0" = Upward "1" = Downward

Designation in signal ID list	Data bit width	Meaning
Out_G1_CNT1	1 bit	Signal ID of output

The same applies for the other counter blocks making allowance for the naming convention:

• "B<Block number>_G<Group number>_CNT<Number>_<Input number>..."
• "Out_G<Group number>_CNT<Number>..."

	Parameterizable special module (PSM) control unit component description		GF54.21-S-5005TRA
	Overview of system components for parameterizable special module (PSM)		GF54.21-S-9998TRA