Theory Of Operation

This DTC indicates a failure was detected in one or more of the following five monitored internal computing processes:

• Computational failures of the Transmission Control Module (TCM) which are related to the speed signal monitoring. All rationality checks of speed sensor signals are calculated in a complement form. The failure is detected if the complementary signals do not correspond.
• Failures in the measurement of battery voltage. To detect measurement failures, the battery voltage is measured on two separated paths inside the TCM. If the Battery Voltage or Switched Battery Voltage is out of range or the voltage drop of Switched Battery Voltage is too high, an error entry has to be made.
• Detection that the second microprocessor has disabled actuators for the High Side Switch (HSS) and Low Side Switch (LSS) because the second microprocessor has detected a main microprocessor calculation failure. The gradient in transmission output speed monitoring of the second microprocessor may be disabled under certain conditions by the main Central Processing Unit (CPU). To prevent a false calculation of this enable/disable condition, a Level 2 safety calculation is performed by the main microprocessor and is verified by the second microprocessor. If this verification fails, the second microprocessor disables the HSS and LSS by deactivating each independent output line. A failure is detected if results of the Level 2 calculation of main CPU differs from precalculated results in the second CPU or if a driver warning is expected to be sent by the main CPU but second CPU did not receive the acknowledgment.
• Communication failures between the main microprocessor and the second microprocessor. Both microprocessors communicate with each other via a serial link. The failure is detected if the communication between the main microprocessor and the second microprocessor fails.
• The second microprocessor has disabled the HSS and LSS actuator supply because it has detected an internal failure.