Theory Of Operation

Core Monitoring:  Core Monitoring checks the functionality of the Analog to Digital Converter (ADC), SPI-BUS, Error Correction Code (ECC) and the setting of the Central Processing Unit (CPU) configuration registers. For the ADC functionality check different HW signals are measured by the ADC circuit and compared against configured voltage limits or other HW signals. The monitoring for the SPI functionality is done by evaluating the SPI status of the last SPI data transmissions between the CPU and the ASIC. By system design, it is ensured that there is a periodically SPI traffic between those 3 HW components. To check the functionality of the ECC many kinds of tests are performed on randomly changing memory addresses. The monitoring SW will simulate memory cells reside in RAM and ROM that show an inconsistent memory content (like shown by a defect RAM cell). If these memory cells are read again the ECC will detect the differences and correct the memory contents as stored in the appropriate ECC data. The occurrence and functionality of the Interrupt Service Routine (ISR) is tested which will be automatically called if a memory cell with an invalid content is read during normal operation of the TCM. For the test of the correct setup of the CPU configuration registers the contents of these registers are periodically compared against the requested values.

Level 2 Monitoring:  Level 2 functions are monitoring and validating safety related functions. This is done by a way of computation, check of value ranges and other measures. The level 2 monitoring is a countermeasure against permanent and sporadic failures of the microcontroller or software. The Level 2 monitoring checks for faults reported by functions containing a level 2 calculation.